PLDA has announced the immediate availability of its PCIe Gen 2 field programmable gate array. Designed for Altera (News - Alert) Stratix II GX FPGAs, the PLDA PCIe IP Core is 100 percent compliant with Revision 2.0 of the PCIe specification.

 

Key features of the PLDA PCIe Gen 2 IP Core for Altera Stratix II GX FPGAs include application layer with up to 8 automated DMA engines, high performance interface that allows up to 16 simultaneous outstanding requests, and complete support for scatter-gather.

 

With this launch PLDA extends the performance and advantages of its PCIe for ASIC IP core into FPGAs.

 

Dave Greenfield, Altera’s senior director product marketing for high-end FPGAs, said in a statement that PLDA’s IP support for PCI Express Gen2 targeting Altera’s Stratix II GX FPGAs builds on the strong existing relationship between Altera and PLDA. He noted that this solution highlights the compelling performance attributes of Stratix II GX FPGAs for addressing high performance system requirements.

 

Stephane Hauradou, CTO for PLDA pointed out that PLDA and Altera have been working together for almost 12 years now and PLDA has a history of supporting the whole range of PCI-related busses on Altera FPGAs. PCI-SIG hasn’t started the official compliance testing for PCIe 2.0, yet PLDA’s PCIe Gen 2 IP has already obtained the PCI-SIG “FYI” testing on Altera Stratix II GX FPGAs.

 

This announcement signifies another in a series of industry firsts for PLDA and the PCIe Gen 2 bus interface. In May 2007, PLDA reportedly launched and provided a demonstration of its PCIe Gen 2 for ASIC, displaying the highest speed, functioning PCIe IP core on the market

 

PLDA designs and sells a wide range of ASIC and FPGA IP solutions including bus controllers, bridges and audio/video IPs.